#include <io.h>

#ifndef __ISP_1362_REGS_H_
#define __ISP_1362_REGS_H_
//#define IOADDR_ISP_1362_BSR(base)             __IO_CALC_ADDRESS_DYNAMIC(base,0x00)

/* Peripheral command phase */
#define IOADDR_ISP_1362_PERIPHERAL_COMMAND_BSR(base)    __IO_CALC_ADDRESS_DYNAMIC(base,12)
#define IOWR_ISP_1362_PERIPHERAL_COMMAND(base,data)     IOWR_16DIRECT(base,12,data)
/* Peripheral data phase */
#define IOADDR_ISP_1362_PERIPHERAL_DATA_BSR(base)       __IO_CALC_ADDRESS_DYNAMIC(base,8)
#define IORD_ISP_1362_PERIPHERAL_DATA(base)             IORD_16DIRECT(base,8)
#define IOWR_ISP_1362_PERIPHERAL_DATA(base,data)        IOWR_16DIRECT(base,8,data)
#define IOWR_ISP_1362_PERIPHERAL_8_DATA(base,data)        IOWR_8DIRECT(base,8,data)
/* Peripheral register define */

/* Initialization commands */
#define ISP_1362_DcEndpointConfigration_EP0_OUT_Write_reg           0x20     //1 byte
#define ISP_1362_DcEndpointConfigration_EP0_IN_Write_reg            0x21     //1 byte
#define ISP_1362_DcEndpointConfigration_EPx_Write_reg(index)        0x21+index     //1 byte
#define ISP_1362_DcEndpointConfigration_EP0_OUT_Read_reg            0x30     //1 byte
#define ISP_1362_DcEndpointConfigration_EP0_IN_Read_reg             0x31     //1 byte
#define ISP_1362_DcEndpointConfigration_EPx_Read_reg(index)         0x31+index     //1 byte
#define ISP_1362_DcAddress_Write_reg                                0xb6     //1 byte
#define ISP_1362_DcAddress_Read_reg                                 0xb7     //1 byte
#define ISP_1362_DcMode_Write_reg                                   0xb8     //1 byte
#define ISP_1362_DcMode_Read_reg                                    0xb9     //1 byte
#define ISP_1362_DcHardwareConfiguration_Write_reg                  0xba     //2 byte
#define ISP_1362_DcHardwareConfiguration_Read_reg                   0xbb     //2 byte
#define ISP_1362_DcInterrputEnable_Write_reg                        0xc2     //4 byte
#define ISP_1362_DcInterrputEnable_Read_reg                         0xc3     //4 byte
#define ISP_1362_DcDMAConfiguration_Write_reg                       0xf0     //2 byte
#define ISP_1362_DcDMAConfiguration_Read_reg                        0xf1     //2 byte
#define ISP_1362_DcDMACounter_Write_reg                             0xf2     //2 byte
#define ISP_1362_DcDMACounter_Read_reg                              0xf3     //2 byte
#define ISP_1362_DCReset_reg                                        0xf6     //0 byte
/* Data flow commands */
#define ISP_1362_EP0_IN_Buffer_Write_reg                            0x01       //<64 byte
#define ISP_1362_EPx_Buffer_Write_reg(index)                        0x01+index //iso < 1023 byte
                                                                               //intr<64 byte
#define ISP_1362_EP0_OUT_Buffer_Read_reg                            0x10       //<64 byte
#define ISP_1362_EPx_Buffer_Read_reg(index)                         0x11+index //iso < 1023 byte
                                                                               //intr<64 byte 
#define ISP_1362_EP0_OUT_STALL_reg                                  0x40        //0 byte
#define ISP_1362_EP0_IN_STALL_reg                                   0x41        //0 byte
#define ISP_1362_EPx_STALL_reg(index)                               0x41+index  //0 byte

#define ISP_1362_DcEndpointStatus_EP0_OUT_Read_reg                     0x50        //1 byte
#define ISP_1362_DcEndpointStatus_EP0_IN_Read_reg                      0x51        //1 byte      
#define ISP_1362_DcEndpointStatus_EPx_Read_reg(index)                  0x51+index  //1 byte                             
#define ISP_1362_EP0_IN_Validate_Buffer_reg                         0x61        //0 byte
#define ISP_1362_EPx_Validate_Buffer_reg(index)                     0x61+index  //0 byte
#define ISP_1362_EP0_OUT_Clear_Buffer_reg                           0x70        //0 byte
#define ISP_1362_EPx_Clear_Buffer_reg(index)                        0x71+index  //0 byte
#define ISP_1362_EP0_OUT_UNSTALL_reg                                0x80        //0 byte
#define ISP_1362_EP0_IN_UNSTALL_reg                                 0x81        //0 byte
#define ISP_1362_EPx_UNSTALL_reg(index)                             0x81+index  //0 byte
#define ISP_1362_DcEndpointStatusImage_EP0_OUT_Read_reg             0xd0        //1 byte
#define ISP_1362_DcEndpointStatusImage_EP0_IN_Read_reg              0xd1        //1 byte
#define ISP_1362_DcEndpointStatusImage_EPx_Read_reg(index)          0xd1+index  //1 byte
#define ISP_1363_Acknowledge_Set_Up                                 0xf4        //0 byte
/* command and register */
#define ISP_1362_DcErrorCode_EP0_OUT_Read_reg                       0xa0        //1 byte
#define ISP_1362_DcErrorCode_EP0_IN_Read_reg                        0xa1        //1 byte
#define ISP_1362_DcErrorCode_EPx_Read_reg(index)                    0xa1+index  //1 byte
#define ISP_1362_Unlock_Device_Write_reg                            0xb0        //2 byte
#define ISP_1362_DcScratch_Write_reg                                0xb2        //2 byte
#define ISP_1362_DcScratch_Read_reg                                 0xb3        //2 byte
#define ISP_1362_DcFrameNumber_Read_reg                             0xb4        //1 or 2 byte
#define ISP_1362_DcChipID_Read_reg                                  0xb5        //2 byte
#define ISP_1362_DcInterrupt_Read_reg                               0xc0        //4 byte

/* DcEndpointConfiguration reg */
#define DcEndpointConfiguration_FIFOEN_MSK                          0x80
#define DcEndpointConfiguration_FIFOEN_OFST                         7
#define DcEndpointConfiguration_EPDIR_MSK                           0x40
#define DcEndpointConfiguration_EPDIR_OFST                          6
#define DcEndpointConfiguration_DBLBUF_MSK                          0x20
#define DcEndpointConfiguration_DBLBUF_OFST                         5
#define DcEndpointConfiguration_FFOISO_MSK                          0x10
#define DcEndpointConfiguration_FFOISO_OFST                        4
#define DcEndpointConfiguration_FFOSZ_8_MSK                         0x00
#define DcEndpointConfiguration_FFOSZ_16_MSK                        0x01
#define DcEndpointConfiguration_FFOSZ_32_MSK                        0x02
#define DcEndpointConfiguration_FFOSZ_64_MSK                        0x03
/* DcAdress reg */
#define DcAddress_DEVEN_MSK                                         0x80
#define DcAddress_DEVEN_OFST                                        7
/* DcMode reg */
#define DcMode_GOSUSP_MSK                                           0x20
#define DcMode_GOSUSP_OFST                                          5
#define DcMode_INTENA_MSK                                           0x08
#define DcMode_INTENA_OFST                                          3
#define DcMode_DBGMOD_MSK                                           0x04
#define DcMode_DBGMOD_OFST                                          2
#define DcMode_SOFTCT_MSK                                           0x01
#define DcMode_SOFTCT_OFST                                          0
/* DcHardwareConfiguration */
#define DcHardwareConfiguration_EXTPUL_MSK                          0x4000
#define DcHardwareConfiguration_EXTPUL_OFST                         14
#define DcHardwareConfiguration_NOLAZY_MSK                          0x2000
#define DcHardwareConfiguration_NOLAZY_OFST                         13
#define DcHardwareConfiguration_CLKRUN_MSK                          0x1000
#define DcHardwareConfiguration_CLKRUN_OFST                         12
#define DcHardwareConfiguration_CLKDIV_1_48MHz                      0x0
#define DcHardwareConfiguration_CLKDIV_4_12MHz                      0x3
#define DcHardwareConfiguration_DAKOLY_MSK                          0x0080
#define DcHardwareConfiguration_DAKOLY_OFST                         7
#define DcHardwareConfiguration_DRQPOL_MSK                          0x0040
#define DcHardwareConfiguration_DRQPOL_OFST                         6
#define DcHardwareConfiguration_DAKPOL_MSK                          0x0020
#define DcHardwareConfiguration_DAKPOL_OFST                         5
#define DcHardwareConfiguration_WKUPCS_MSK                          0x0008
#define DcHardwareConfiguration_WKUPCS_OFST                         3
#define DcHardwareConfiguration_INTLVL_MSK                          0x0002
#define DcHardwareConfiguration_INTLVL_OFST                         1
#define DcHardwareConfiguration_INTPOL_MSK                          0x0001
#define DcHardwareConfiguration_INTPOL_OFST                         0
/* DcInterruptEnable reg */
#define DcInterruptEnable_IERST_MSK                                 0x0001
#define DcInterruptEnable_IERST_OFST                                0
#define DcInterruptEnable_IERSM_MSK                                 0x0002
#define DcInterruptEnable_IERSM_OFST                                1
#define DcInterruptEnable_IESUSP_MSK                                0x0004
#define DcInterruptEnable_IESUSP_OFST                               2
#define DcInterruptEnable_IEEOT_MSK                                 0x0008
#define DcInterruptEnable_IEEOT_OFST                                3
#define DcInterruptEnable_IESOF_MSK                                 0x0010
#define DcInterruptEnable_IESOF_OFST                                4
#define DcInterruptEnable_IEPSOF_MSK                                0x0020
#define DcInterruptEnable_IEPSOF_OFST                               5
#define DcInterruptEnable_SP_IEEOT_MSK                              0x0040
#define DcInterruptEnable_SP_IEEOT_OFST                             6
#define DcInterruptEnable_IEP0OUT_MSK                               0x0100
#define DcInterruptEnable_IEP0OUT_OFST                              8
#define DcInterruptEnable_IEP0IN_MSK                                0x0200
#define DcInterruptEnable_IEP0IN_OFST                               9
#define DcInterruptEnable_IEPxIN_MSK(index)                         (0x0200<<index)
#define DcInterruptEnable_IEPxIN_OFST(index)                        9+index
/* DcDMAConfiguration */
#define DcDMAConfiguration_CNTREN_MSK                               0x8000
#define DcDMAConfiguration_CNTREN_OFST                              15
#define DcDMAConfiguration_SHORTP_MSK                               0x4000
#define DcDMAConfiguration_SHORTP_OFST                              14
#define DcDMAConfiguration_DMAEN_MSK                                0x0008
#define DcDMAConfiguration_BURSTL_1_MSK                             0x0
#define DcDMAConfiguration_BURSTL_4_MSK                             0x1
#define DcDMAConfiguration_BURSTL_8_MSK                             0x2
#define DcDMAConfiguration_BURSTL_16_MSK                            0x3
#define DcDMAConfiguration_DMAEN_OFST                               3
#define DcDMAConfiguration_EPDIX_EP1_MSK                            0x0020
#define DcDMAConfiguration_EPDIX_EP2_MSK                            0x0030
#define DcDMAConfiguration_EPDIX_EP3_MSK                            0x0040
#define DcDMAConfiguration_EPDIX_EP4_MSK                            0x0050      
/* DcDMACounter reg */
/* DcEndpointStatus reg */
#define DcEndpointStatus_EPSTAL_MSK									0x80
#define DcEndpointStatus_EPSTAL_OFST								7
#define DcEndpointStatus_EPFULL1_MSK								0x40
#define DcEndpointStatus_EPFULL1_OFST								6
#define DcEndpointStatus_EPFULL0_MSK								0x20
#define DcEndpointStatus_EPFULL0_OFST								5
#define DcEndpointStatus_DATA_PID_MSK								0x10
#define DcEndpointStatus_DATA_PID_OFST								4
#define DcEndpointStatus_OVERWRITE_MSK								0x08
#define DcEndpointStatus_OVERWRITE_OFST								3
#define DcEndpointStatus_SETUPT_MSK									0x04
#define DcEndpointStatus_SETUPT_OFST								2
#define DcEndpointStatus_CPUBUF_MSK									0x02
#define DcEndpointStatus_CPUBUF_OFST								1
/* DcErrorCode reg */
#define DcErrorCode_UNREAD_MSK										0x80
#define DcErrorCode_UNREAD_OFST										7
#define DcErrorCode_DATA01_MSK										0x40
#define DcErrorCode_DATA01_OFST										6
#define DcErrorCode_RTOK_MSK										0x01
#define DcErrorCode_RTOK_OFST										0
	/* error code */
#define NoError														(0x0<<1)
#define PIDError													(0x1<<1)
#define PIDUnknown													(0x2<<1)
#define UnexpectedPacket											(0x3<<1)
#define TokenCRCError												(0x4<<1)
#define DataCRCError												(0x5<<1)
#define TimeOutError												(0x6<<1)
#define BabbleError													(0x7<<1)
#define UnexpectedEndOfPacket										(0x8<<1)
#define NAK															(0x9<<1)
#define SentStall													(0xa<<1)
#define OverFlow													(0xb<<1)
#define SentEmptyPacket												(0xc<<1)
#define BitStuffingError											(0xd<<1)
#define SyncError													(0xe<<1)
#define WrongToggleBit												()xf<<1)
/* DcFrameNumber reg */
/* DcChipID */
/* DcInterrupt reg */
#define DcInterrupt_EP4_MSK											0x2000
#define DcInterrupt_EP4_OFST										13
#define DcInterrupt_EP3_MSK											0x1000
#define DcInterrupt_EP3_OFST										12
#define DcInterrupt_EP2_MSK											0x0800
#define DcInterrupt_EP2_OFST										11
#define DcInterrupt_EP1_MSK											0x0400
#define DcInterrupt_EP1_OFST										10
#define DcInterrupt_EP0IN_MSK										0x0200
#define DcInterrupt_EP0IN_OFST										9
#define DcInterrupt_EP0OUT_MSK										0x0100
#define DcInterrupt_EP0OUT_OFST										8
#define DcInterrupt_BUSTAUS_MSK										0x0080
#define DcInterrupt_BUSTAUS_OFST									7
#define DcInterrupt_SP_EOT_MSK										0x0040
#define DcInterrupt_SP_EOT_OFST										6
#define DcInterrupt_PSOF_MSK										0x0020
#define DcInterrupt_PSOF_OFST										5
#define DcInterrupt_SOF_MSK											0x0010
#define DcInterrupt_SOF_OFST										4
#define DcInterrupt_EOT_MSK											0x0008
#define DcInterrupt_EOT_OFST										3
#define DcInterrupt_SUSPND_MSK										0x0004
#define DcInterrupt_SUSPND_OFST										2
#define DcInterrupt_RESUME_MSK										0x0002
#define DcInterrupt_RESUME_OFST										1
#define DcInterrupt_RESET_MSK										0x0001
#define DcInterrupt_RESET_OFST										0
 

#endif
